Мне нужно перевести VHDL код в Verilog
Вот отрывок моего VHDL кода, и его нужно перевести в Verilog, под стандарты 2001. Моя основная пробела состоит в наследовании компонент, я нигде не нашёл информации как это правильно сделать в Verilog. Т.к. в Verilog нельзя делать вложенные модули, то как передать некоторые переменные в один модуль из другого. А ещё вопрос, почему сигналы и константы нельзя объявлять глобально?
architecture behavior of CPLD_CONTROL_tb_func is
component CPLD_CONTROL
generic
(
C_SIMULATION : boolean := false;
C_LEDS_QUANTITY : natural := 24;
C_TEMP_SENSOR_PO_WL : natural := 16;
C_TEMPERATURE_DATA_WL : natural := 13;
C_MAX_TEMP : real := 40.0
);
port
(
CLK_IN : in std_logic;
PGOOD_All_bus_IN : in std_logic_vector ((C_LEDS_QUANTITY+1-1) downto 0);
KEY_CPLD_IN : in std_logic_vector (3 downto 0);
Temp_sensor_SO_IN : in std_logic;
-- Power enable outputs
EN_ANALOG_PWR_OUT : out std_logic;
EN_DIGITAL_3V3_OUT : out std_logic;
EN_5V0_POWER_OUT : out std_logic;
EN_VCC_2V5_OUT : out std_logic;
EN_VCC_1V0_INT_OUT : out std_logic;
-- Front LEDs outputs
LED_CPLD_0_RED_OUT,
LED_CPLD_1_GREEN_OUT,
LED_CPLD_2_RED_OUT,
LED_CPLD_3_GREEN_OUT : out std_logic;
-- LEDs control outputs
LED_DRIVER_CLK_OUT : out std_logic;
LED_DRIVER_SDI_OUT : out std_logic := '0';
LED_DRIVER_LE_OUT : out std_logic;
-- Temperature sensor control outputs
Temp_sensor_CS_OUT : out std_logic;
Temp_sensor_SCK_OUT : out std_logic;
-- PROG B output
FPGA_PROG_B_OUT : out std_logic
);
end component;
component LED_driver
generic
(
C_N : natural := 16
);
port
(
LED_Clk, LED_LE, LED_SDI : in std_logic := '0';
LED_OE : in std_logic := '1';
LED_SDO : out std_logic;
LED_PO : out std_logic_vector (C_N-1 downto 0)
);
end component;
component Temp_sensor_model
generic
(
C_TEMP_SENSOR_PO_WL : natural := 16;
C_TEMP_SENSOR_DATA_WL : natural := 13
);
port
(
Temp_sensor_Data_IN : in std_logic_vector ((C_TEMP_SENSOR_DATA_WL-1) downto 0) := (others => '0')
Temp_sensor_SCK_IN : in std_logic := '0';
Temp_sensor_CS_IN : in std_logic := '1';
Temp_sensor_SO_OUT : out std_logic
);
end component;
-- Constant declaration
constant CLK_PERIOD_TB_const : time := 25 ns; -- 40 MHz
-- Signal declaration
signal CLK_TB_signal : std_logic := '0';
signal Test_PGOOD_All_bus_TB_signal : std_logic_vector (C_LEDS_QUANTITY_TB+1-1 downto 0) := (others => '0');
signal Test_KEY_CPLD_TB_signal : std_logic_vector (3 downto 0) := (others => '1');
signal EN_Power_TB_signal : std_logic;
signal LED_Clk_TB_signal : std_logic;
signal LED_LE_TB_signal : std_logic;
signal LED_SDI_TB_signal : std_logic;
signal Temp_sensor_SO_TB_signal : std_logic;
signal Temp_sensor_CS_TB_signal : std_logic;
signal Temp_sensor_SCK_TB_signal : std_logic;
signal Temp_sensor_Data_TB_signal : std_logic_vector ((C_TEMP_SENSOR_DATA_WL_TB-1) downto 0) := ((C_TEMP_SENSOR_DATA_WL_TB-1) => '1', others => '0');
begin
-- Simulation procedures
CPLD_CONTROL_inst: CPLD_CONTROL
generic map
(
C_SIMULATION => C_SIMULATION_TB,
C_LEDS_QUANTITY => C_LEDS_QUANTITY_TB,
C_TEMP_SENSOR_PO_WL => C_TEMP_SENSOR_PO_WL_TB,
C_TEMPERATURE_DATA_WL => C_TEMP_SENSOR_DATA_WL_TB,
C_MAX_TEMP => C_MAX_TEMP_TB
)
port map
(
-- Clock input
CLK_IN => CLK_TB_signal,
-- Power control inputs
PGOOD_All_bus_IN => Test_PGOOD_All_bus_TB_signal,
-- User switch inputs
KEY_CPLD_IN => Test_KEY_CPLD_TB_signal,
-- LEDs control intputs
-- LED_DRIVER_SDO_IN => LED_SDO_TB_signal,
-- Temperature sensor data input
Temp_sensor_SO_IN => Temp_sensor_SO_TB_signal,
-- Power enable outputs
EN_ANALOG_PWR_OUT => EN_Power_TB_signal,
EN_DIGITAL_3V3_OUT => open,
EN_5V0_POWER_OUT => open,
EN_VCC_2V5_OUT => open,
EN_VCC_1V0_INT_OUT => open,
-- Front LEDs outputs
LED_CPLD_0_RED_OUT => open,
LED_CPLD_1_GREEN_OUT => open,
LED_CPLD_2_RED_OUT => open,
LED_CPLD_3_GREEN_OUT => open,
-- LEDs control outputs
LED_DRIVER_CLK_OUT => LED_Clk_TB_signal,
LED_DRIVER_SDI_OUT => LED_SDI_TB_signal,
LED_DRIVER_LE_OUT => LED_LE_TB_signal,
-- Temperature sensor control outputs
Temp_sensor_CS_OUT => Temp_sensor_CS_TB_signal,
Temp_sensor_SCK_OUT => Temp_sensor_SCK_TB_signal,
-- PROG B output
FPGA_PROG_B_OUT => open
);
---------------------------------------------------------------------------------------------------------
RTL_LED_driver: LED_driver
generic map
(
C_N => C_LEDS_QUANTITY_TB
)
port map
(
LED_Clk => LED_Clk_TB_signal,
LED_LE => LED_LE_TB_signal,
LED_OE => '0',
LED_SDI => LED_SDI_TB_signal,
LED_SDO => open,
LED_PO => open
);
---------------------------------------------------------------------------------------------------------
Behavioral_Temp_sensor_model: Temp_sensor_model
generic map
(
C_TEMP_SENSOR_PO_WL => C_TEMP_SENSOR_PO_WL_TB,
C_TEMP_SENSOR_DATA_WL => C_TEMP_SENSOR_DATA_WL_TB
)
port map
(
Temp_sensor_Data_IN => Temp_sensor_Data_TB_signal,
Temp_sensor_SCK_IN => Temp_sensor_SCK_TB_signal,
Temp_sensor_CS_IN => Temp_sensor_CS_TB_signal,
Temp_sensor_SO_OUT => Temp_sensor_SO_TB_signal
);
---------------------------------------------------------------------------------------------------------
-- Clock
CLK_TB_signal <= not CLK_TB_signal after CLK_PERIOD_TB_const/2;
---------------------------------------------------------------------------------------------------------
GEN_POWER_CRASH: if (C_CRASH_TYPE_TB = 0 or C_CRASH_TYPE_TB = 2) generate
TEST_POWER_GOOD: process -- '1' - ok, '0' - fail
begin
Test_PGOOD_All_bus_TB_signal <= B"0_0000_0000_0000_0000_0000_0000";
wait for 2.8 us;
Test_PGOOD_All_bus_TB_signal <= B"1_1111_1111_1111_1111_1111_1111";
-- wait for 1700 ms;
wait for 7.2 us;
Test_PGOOD_All_bus_TB_signal <= B"0_1011_1111_1111_1111_1111_1110";
wait on EN_Power_TB_signal;
wait for 50 ns;
Test_PGOOD_All_bus_TB_signal <= B"0_0000_0000_0000_0000_0000_0000";
wait;
end process;
Ниже я представлю свой verilog код, однако в нём будет много ошибок, в том числе из-за непонимания как это можно переделать. Чтобы прояснить ещё ситуацию, я не прошу написать мне весь код, а всего лишь объяснить мне кусок кода или дать источник информации, где я смогу понятным языком прочитать про наследование.
`timescale 1 ns / 1 ps
module CPLD_CONTROL_tb_func #(
parameter C_SIMULATION_TB = 1'b1,
parameter C_LEDS_QUANTITY_TB = 24,
parameter C_CRASH_TYPE_TB = 1,
parameter C_TEMP_SENSOR_DATA_WL_TB = 13,
parameter C_TEMP_SENSOR_PO_WL_TB = 16,
parameter real C_MAX_TEMP_TB = 40.0
)();
`define CLK_PERIOD_TB_const = 25;
reg CLK_TB_signal = 1'b0;
reg [C_LEDS_QUANTITY_TB+1-1:0]Test_PGOOD_All_bus_TB_signal = {C_LEDS_QUANTITY_TB{1'b0}};
reg [3:0]Test_KEY_CPLD_TB_signal;
reg EN_Power_TB_signal;
reg LED_Clk_TB_signal;
reg LED_LE_TB_signal;
reg LED_SDI_TB_signal;
reg Temp_sensor_SO_TB_signal;
reg Temp_sensor_CS_TB_signal;
reg Temp_sensor_SCK_TB_signal;
reg [C_TEMP_SENSOR_DATA_WL_TB-1:0] Temp_sensor_Data_TB_signal = {C_TEMP_SENSOR_DATA_WL_TB-1{1'b0}};
module CPLD_CONTROL_inst #(
parameter C_SIMULATION,
C_LEDS_QUANTITY,
C_TEMP_SENSOR_DATA_WL,
C_TEMP_SENSOR_PO_WL,
C_MAX_TEMP = C_MAX_TEMP_TB
) (
input wire CLK_IN,
PGOOD_All_bus_IN,
KEY_CPLD_IN,
Temp_sensor_SO_IN,
output wire EN_ANALOG_PWR_OUT,
EN_DIGITAL_3V3_OUT,
EN_5V0_POWER_OUT,
EN_VCC_2V5_OUT,
EN_VCC_1V0_INT_OUT,
LED_CPLD_0_RED_OUT,
LED_CPLD_1_GREEN_OUT,
LED_CPLD_2_RED_OUT,
LED_CPLD_3_GREEN_OUT,
LED_DRIVER_CLK_OUT,
LED_DRIVER_SDI_OUT,
LED_DRIVER_LE_OUT,
Temp_sensor_CS_OUT,
Temp_sensor_SCK_OUT,
FPGA_PROG_B_OUT
);
endmodule
module RTL_LED_driver #(
parameter C_N
)(
output wire LED_Clk,
LED_LE,
LED_OE,
LED_SDI,
LED_SDO,
LED_PO
);
endmodule
module Behavioral_Temp_sensor_model #(
parameter C_TEMP_SENSOR_PO_WL,
C_TEMP_SENSOR_DATA_WL,
)(
input wire Temp_sensor_Data_IN,
Temp_sensor_SCK_IN,
Temp_sensor_CS_IN,
output wire Temp_sensor_SO_OUT
);
always @() begin
#CLK_PERIOD_TB_const/2 CLK_TB_signal = ~CLK_TB_signal
end;
always @(posedge CLK_IN) begin
if (C_CRASH_TYPE_TB == 0 || C_CRASH_TYPE_TB == 2) begin
Test_PGOOD_All_bus_TB_signal <= 32'h00000000;
#3;
Test_PGOOD_All_bus_TB_signal <= 32'hFFFFFFFF;
#7;
Test_PGOOD_All_bus_TB_signal <= 32'hBFFFFFFE;
@(posedge EN_Power_TB_signal);
#5;
Test_PGOOD_All_bus_TB_signal <= 32'h00000000;
end
end
always @(posedge CLK_IN) begin
#5;
if (C_CRASH_TYPE_TB == 0) begin
Temp_sensor_Data_TB_signal <= {C_TEMP_SENSOR_DATA_WL_TB{1'b0}} + ((C_MAX_TEMP_TB - 1.0) / 0.0625);
end else begin
Temp_sensor_Data_TB_signal <= {C_TEMP_SENSOR_DATA_WL_TB{1'b0}} + ((C_MAX_TEMP_TB + 1.0) / 0.0625);
end
end
always @(posedge CLK_IN) begin
if (C_CRASH_TYPE_TB == 1) begin
Test_PGOOD_All_bus_TB_signal <= 32'h00000000;
#3;
Test_PGOOD_All_bus_TB_signal <= 32'hFFFFFFFF;
wait on EN_Power_TB_signal;
#5;
Test_PGOOD_All_bus_TB_signal <= 32'h00000000;
end
end
always @(posedge CLK_IN) begin
if (C_CRASH_TYPE_TB == 1) begin
#5;
Temp_sensor_Data_TB_signal <= $sformatf("%0d", (C_MAX_TEMP_TB-1.0) / 0.0625);
#25;
Temp_sensor_Data_TB_signal <= $sformatf("%0d", (C_MAX_TEMP_TB+1.0) / 0.0625);
end
end
always @(posedge CLK_IN) begin
Test_KEY_CPLD_TB_signal <= 4'b1111;
#4;
Test_KEY_CPLD_TB_signal <= 4'b1110;
#1;
Test_KEY_CPLD_TB_signal <= 4'b1100;
#1;
Test_KEY_CPLD_TB_signal <= 4'b1001;
#1;
Test_KEY_CPLD_TB_signal <= 4'b0011;
#1;
Test_KEY_CPLD_TB_signal <= 4'b0111;
#1;
Test_KEY_CPLD_TB_signal <= 4'b1111;
end
endmodule
endmodule