Происходит ли подключение к индикаторам (7ми-сегментным)
Вот код таймера от преподавателя где прописаны единицы и десятки секунд:
-- project Timer: template
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Math_PACK.all;
entity Timer is
port
(
-- module signals
clk_i : in std_logic;
SS_Pin : out SS_array(3 downto 0);
-- simulation signals
Ref_Freq_vp : out std_logic;
cnt_sec_10_carry_vp : out std_logic;
cnt_sec_60_carry_vp : out std_logic;
CLK50_vp : out std_logic;
cnt_sec_10_o_vp : out STD_LOGIC_VECTOR(3 DOWNTO 0);
cnt_sec_60_o_vp : out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end entity;
architecture rtl of Timer is
CONSTANT Input_Freq : natural := 50000000; -- input frequency value
CONSTANT PRESCALER_RATIO : natural := Input_Freq / 10000000; -- sets the counter switching step
CONSTANT PRESCALER_SIZE : natural := f_log2(PRESCALER_RATIO); -- counter size
signal prescaler_s : STD_LOGIC_VECTOR(PRESCALER_SIZE-1 DOWNTO 0);
signal pre_rst_s : std_logic := '0';
signal Ref_Freq_s : std_logic := '0';
signal cnt_sec_10_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal cnt_sec_10_carry_s : std_logic;
signal cnt_sec_6x10_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal cnt_sec_6x10_carry_s : std_logic;
COMPONENT Seven_Segment -- seven-segment indicator
PORT
(
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
Number : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Segment : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
type Number_array is array(natural range <>) of STD_LOGIC_VECTOR(3 DOWNTO 0);
signal Number_s : Number_array(3 DOWNTO 0); -- counter code register
signal Segment_s : SS_array(3 downto 0); -- decrypt code for seven-segment indicator
component Main_PLL -- PLL
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
end component;
signal CLK50_s : STD_LOGIC; -- internal clock
begin
------------------------------------- PLL -----------------------------------
PLL: Main_PLL
port map(
inclk0 => clk_i,
c0 => CLK50_s
);
----------------------------------- PRESCALER -------------------------------
Prescaler : process (CLK50_s)
begin
if (rising_edge(CLK50_s)) then
prescaler_s <= prescaler_s + '1';
pre_rst_s <= '0';
if (prescaler_s = std_logic_vector(to_unsigned(PRESCALER_RATIO-1, PRESCALER_SIZE))) then
prescaler_s <= (others => '0');
pre_rst_s <= '1';
end if;
end if;
end process;
Ref_Freq_s <= pre_rst_s;
-------------------------------- second counter --------------------------------------
cnt_1sec : process (CLK50_s)
begin
if (rising_edge(CLK50_s)) then
-- counter up to 10
-- counter states change on CLK50_s edge with the Ref_Freq_s frequency
if (Ref_Freq_s = '1') then
cnt_sec_10_s <= cnt_sec_10_s + '1';
if (cnt_sec_10_s = std_logic_vector(to_unsigned(9, 4))) then
cnt_sec_10_s <= (others => '0');
end if;
cnt_sec_10_carry_s <= '0';
if (cnt_sec_10_s = std_logic_vector(to_unsigned(8, 4))) then
cnt_sec_10_carry_s <= '1';
end if;
end if;
end if;
end process;
----------------------------- ten second counter ------------------------------------
cnt_10sec : process (CLK50_s)
begin
if (rising_edge(CLK50_s)) then
-- counter up to 6 (from 0 to 5). Increases every 10 values (use cnt_sec_10_carry_s signal for this)
if (Ref_Freq_s = '1' and cnt_sec_10_carry_s = '1') then
cnt_sec_6x10_s <= cnt_sec_6x10_s + '1';
if (cnt_sec_6x10_s = std_logic_vector(to_unsigned(5, 4))) then
cnt_sec_6x10_s <= (others => '0');
end if;
cnt_sec_6x10_carry_s <= '0';
if (cnt_sec_6x10_s = std_logic_vector(to_unsigned(4, 4))) then
cnt_sec_6x10_carry_s <= '1';
end if;
end if;
end if;
end process;
----------------------------- seven-segment indicator --------------------------------
-- decrypt code from the counter into signals for seven-segment indicator
process (CLK50_s)
begin
if (rising_edge(CLK50_s)) then
Number_s(0) <= cnt_sec_10_s;
Number_s(1) <= cnt_sec_6x10_s;
Number_s(2) <= b"0011";
Number_s(3) <= b"0100";
end if;
end process;
Indicator: For I in 0 to 3 generate
SS_Display: Seven_Segment
port map(
clock => CLK50_s,
enable => '1',
Number => Number_s(I),
Segment => Segment_s(I)
);
SS_Pin(I) <= Segment_s(I);
End generate;
----------------------------- simulation signals --------------------------------
CLK50_vp <= CLK50_s;
Ref_Freq_vp <= Ref_Freq_s;
cnt_sec_10_carry_vp <= cnt_sec_10_carry_s;
cnt_sec_60_carry_vp <= cnt_sec_6x10_carry_s;
cnt_sec_10_o_vp <= cnt_sec_10_s;
cnt_sec_60_o_vp <= cnt_sec_6x10_s;
end rtl;
И меня интересует конкретно этот момент:
----------------------------- seven-segment indicator --------------------------------
-- decrypt code from the counter into signals for seven-segment indicator
process (CLK50_s)
begin
if (rising_edge(CLK50_s)) then
Number_s(0) <= cnt_sec_10_s;
Number_s(1) <= cnt_sec_6x10_s;
Number_s(2) <= b"0011";
Number_s(3) <= b"0100";
end if;
end process;
Indicator: For I in 0 to 3 generate
SS_Display: Seven_Segment
port map(
clock => CLK50_s,
enable => '1',
Number => Number_s(I),
Segment => Segment_s(I)
);
SS_Pin(I) <= Segment_s(I);
End generate;
Вопрос такой, происходит ли здесь конкретное подключение индикаторов 7-сегментных ?
Эта прога от препода и она вроде как работает
Но я не пойму, есть ли тут подключение к индикаторам ?